1. Field of the Invention
The present invention generally relates to a nonvolatile semiconductor memory device comprising a nonvolatile data register, and more specifically, to a technology of a high-performance system without requiring an additional system setting process to set the initial state to be at the previous state when power is turned on.
2. Description of the Related Art
FIG. 1 is a circuit diagram illustrating a data register of a conventional SRAM. Here, a plurality of data registers are connected to form a Static Random Access Memory (hereinafter, referred to as “SRAM”).
The data register of FIG. 1 comprises a pull-up driving unit 2, a pull-down driving unit 4 and a data input/output unit 6.
The pull-up driving unit 2 comprises PMOS transistors PT1 and PT2 which have gates cross-coupled with a latch structure.
The pull-down driving unit 4 comprises NMOS transistors NT1 and NT2 which have gates cross-coupled with a latch structure.
The data input/output unit 6 comprises switches NT3 and NT4 configured to selectively input and output data with bit lines BL and /BL depending on a voltage applied to a word line WL. Here, the switches NT3 and NT4 are NMOS transistors which have gates connected to the word line WL.
The operation of the above-described data register of the conventional SRAM is explained below.
In a read mode, when high level data are loaded on the true bit line BL and a driving voltage Vpp is applied to the word line WL, the switches NT3 and NT4 of the data input/output unit 4 are turned on. Here, the complement bit line /BL is set at a low level.
In the pull-up driving unit 2, the first PMOS transistor PT1 is turned on, and the second PMOS transistor PT2 is turned off.
In the pull-down driving unit 4, the first NMOS transistor NT1 is turned off, and the second NMOS transistor NT2 is turned on.
Here, when the driving voltage Vpp applied to the word line WL is intercepted, the high level data are latched by the pull-up driving unit 2 and the pull-down driving unit 4.
Meanwhile, in a read mode, when the driving voltage Vpp is applied to the word line WL, the switches NT3 and NT4 of the data input/output unit 6 are turned on.
In the case that high level data are stored, the first PMOS transistor PT1 of the pull-up driving unit 2 is turned on, so that the high level data are loaded on the true bit line BL. Here, the second NMOS transistor NT1 of the pull-down driving unit 4 is turned on to set the complement bit line /BL at a low level.
While the examples concern the case of high level data stored or read, low level data are also stored or read by the same operation as described above.
However, the conventional data register requires additional circuits and steps for a system setting process at a power-on mode.